rev.3.00, apr.14.2 003, page 1 of 10 HAT2175H silicon n channel power mos fet power switching rej03g0006-0300z rev.3.00 apr.14.2003 features ? capable of 8 v gate drive ? low drive current ? high density mounting ? low on-resistance r ds(on) = 33 m ? typ. (at v gs = 10 v) outline lfpak 1 2 3 4 5 1, 2, 3 source 4 gate 5 drain g d sss 4 1 23 5
HAT2175H rev.3.00, apr.14.2 003, page 2 of 10 absolute maximum ratings (ta = 25c) item symbol ratings unit drain to source voltage v dss 100 v gate to source voltage v gss 20 v drain current i d 15 a drain peak current i d(pulse) note1 60 a body-drain diode reverse drain current i dr 15 a avalanche current i ap note 2 15 a avalanche energy e ar note 2 22.5 mj channel dissipation pch note3 15 w channel to case thermal resistance ch-c 8.34 c/w channel temperature tch 150 c storage temperature tstg ?55 to +150 c notes: 1. pw 10 s, duty cycle 1% 2. value at tch = 25 c, rg 50 ? 3. tc = 25 c
HAT2175H rev.3.00, apr.14.2 003, page 3 of 10 electrical characteristics (ta = 25c) item symbol min typ max unit test conditions drain to source breakdown voltage v (br)dss 100 ? ? v i d = 10 ma, v gs = 0 gate to source breakdown voltage v (br)gss 20??v i g = 100 a, v ds = 0 gate to source leak current i gss ?? 10 av gs = 16 v, v ds = 0 zero gate voltege drain current i dss ??1 av ds = 100 v, v gs = 0 gate to source cutoff voltage v gs(off) 4.0 ? 6.0 v v ds = 10 v, i d = 20ma static drain to source on state r ds(on) ? 3342m ? i d = 7.5 a, v gs = 10 v note4 resistance r ds(on) ? 3446m ? i d = 7.5 a, v gs = 8 v note4 forward transfer admittance |y fs |1525?s i d = 7.5 a, v ds = 10 v note4 input capacitance ciss ? 1445 ? pf v ds = 10 v output capacitance coss ? 185 ? pf v gs = 0 reverse transfer capacitance crss ? 61 ? pf f = 1 mhz gate resistance rg ? 0.55 ? ? total gate charge qg ? 21 ? nc v dd = 50 v gate to source charge qgs ? 8 ? nc v gs = 10 v gate to drain charge qgd ? 4.5 ? nc i d = 15 a turn-on delay time t d(on) ?17?nsv gs = 10 v, i d = 7.5 a rise time t r ?8.2?nsv dd ? 30 v turn-off delay time t d(off) ?28?nsr l = 4 ? fall time t f ? 4.7 ? ns rg = 4.7 ? body?drain diode forward voltage v df ? 0.84 1.10 v if = 15 a, v gs = 0 note4 body?drain diode reverse recovery time t rr ? 45 ? ns if = 15 a, v gs = 0 dif/ dt = 100 a/ s notes: 4. pulse test
HAT2175H rev.3.00, apr.14.2 003, page 4 of 10 main characteristics channel dissipation pch (w) case temperature tc ( c) power vs. temperature derating drain to source voltage v (v) ds drain current i (a) d typical output characteristics gate to source voltage v (v) gs drain current i (a) d typical transfer characteristics 20 16 12 8 4 0 246810 20 16 12 8 4 0 2468 10 tc = 75 c 25 c -25 c 40 30 20 10 0 50 100 150 200 v = 10 v pulse test ds v gs = 5.4 v 10 v 8 v 5.8 v 5.6 v 6.0 v 6.2 v 6.4 v pulse test drain to source voltage v (v) ds drain current i (a) d maximum safe operation area 100 10 1 0.1 0.01 0.1 0.3 1 3 10 30 100 500 500 tc = 25 c 1 shot pulse pw = 10 ms 10 s 100 s operation in this area is limited by r ds(on) dc operation 1 ms
HAT2175H rev.3.00, apr.14.2 003, page 5 of 10 gate to source voltage v (v) gs drain to source voltage v (mv) ds(on) drain to source saturation voltage vs. gate to source voltage drain current i (a) d drain to source on state resistance r (m ) ? ds(on) static drain to source on state resistance vs. drain current case temperature tc ( c) static drain to source on state resistance static drain to source on state resistance vs. temperature forward transfer admittance |yfs| (s) drain current i (a) d forward transfer admittance vs. drain current 200 100 20 50 10 30 100 80 60 40 20 -25 0 25 50 75 100 125 150 0 1 10 100 3 1000 500 r (m ) ? ds(on) i d = 10 a i d = 10 a v gs = 8 v 10 v pulse test 330 0.1 1 10 100 0.3 10 100 30 1 0.3 3 0.1 tc = -25 c ds v = 10 v pulse test 75 c 25 c 500 400 300 200 100 0 4 8 12 16 20 pulse test i = 10 a d 2 a 5 a 2 a, 5a 2 a, 5a v = 8 v gs 10 v pulse test
HAT2175H rev.3.00, apr.14.2 003, page 6 of 10 reverse drain current i (a) dr reverse recovery time trr (ns) body-drain diode reverse recovery time capacitance c (pf) drain to source voltage v (v) ds typical capacitance vs. drain to source voltage drain current i (a) d switching time t (ns) switching characteristics 0.1 0.3 1 3 10 30 100 20 50 10 0 1020304050 10000 3000 1000 300 100 30 10 ciss coss crss v = 0 f = 1 mhz gs 100 30 10 1 3 di/dt = 100 a/ s v = 0, ta = 25 c gs 0.3 1 3 10 30 100 0.1 v = 10 v , v = 30 v rg = 4.7 , duty < 1 % gs ds ? 100 250 200 150 100 50 0 20 16 12 8 4 816243240 0 i = 15 a d v gs v ds v dd = 100 v 50 v 25 v v dd = 100 v 50 v 25 v gate charge qg (nc) drain to source voltage v (v) ds gate to source voltage v (v) gs dynamic input characteristics t f t r t d(off) t d(on)
HAT2175H rev.3.00, apr.14.2 003, page 7 of 10 source to drain voltage v (v) sd reverse drain current i dr (a) reverse drain current vs. source to drain voltage d. u. t rg i monitor ap v monitor ds v dd 50 ? vin 15 v 0 i d v ds i ap v (br)ds s l v dd e ar = l ? i ap 2 ? 2 1 v v - v dss dss dd avalanche test circuit avalanche waveform 25 20 15 10 5 25 50 75 100 125 150 0 channel temperature tch ( c) repetitive avalanche energy e (mj) ar maximum avalanche energy vs. channel temperature derating i = 15 a v = 50 v duty < 0.1 % rg > 50 ap dd ? 20 16 12 8 4 0 0.4 0.8 1.2 1.6 2.0 pulse test 5 v v = 0 gs 10 v
HAT2175H rev.3.00, apr.14.2 003, page 8 of 10 pulse width pw (s) normalized transient thermal impedance vs. pulse width normalized transient thermal impedance s (t) 3 1 0.3 0.1 0.03 0.01 10 100 1 m 10 m 100 m 1 10 tc = 25 c d = 1 0.5 0.2 0.1 0.05 0.02 0.01 1shot p ulse dm p pw t d = pw t ch - c(t) = s (t) ? ch - c ch - c = 8.34 c/ w, tc = 25 c vin monitor d.u.t. vin 10 v r l v = 30 v ds tr td(on) vin 90% 90% 10% 10% vout td(off) vout monitor 90% 10% t f switching time test circuit switching time waveform rg
HAT2175H rev.3.00, apr.14.2 003, page 9 of 10 package dimensions 0.25 m 1.3 max 1.0 3.95 1.1 max 4.9 5.3 max 4.0 ?0.2 14 5 4.2 3.3 0? ?8? 0.07 +0.03 ?.04 *0.20 +0.05 ?.03 0.6 +0.25 ?.20 0.25 +0.05 ?.03 6.1 +0.1 ?.3 1.27 *0.40 ?0.06 0.75 max 0.10 package code jedec jeita mass (reference value) lfpak 0.080 g as of january, 2003 unit: mm *ni/pd/au plating
HAT2175H rev.3.00, apr.14.2 003, page 10 of 10 keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but ther e is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation p roduct best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporat ion or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, origin ating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reas ons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest produ ct information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracie s or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas te chnology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp oration assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used un der circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor wh en considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com copyright ? 2003. renesas technology corporation, all rights reserved. printed in japan. colophon 0.0
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